Supervisor:
Stig Munk-Nielsen

Co-Supervisor:
Asger Bjørn Jørgensen

Szymon Beczkowski

Assessment Committee:
Huai Wang(Chair)
Professor Jean-Luc Schanen, Grenoble-INP Univ. Grenoble Alpes
Dr. Ivana Kovacevic, ETH Zürich

Moderator:
Huai Wang

Abstract:

The area of power electronics is crucial to the green energy transition, interfacing the core parts of the energy system and industrial processes. The emergence of new semiconductor materials is a big opportunity to reduce power losses and decrease the size and weight of the power electronics devices, as well as to expand to higher voltage and frequency levels. Integrating the new materials and fully utilizing their properties requires more advanced and automated design methods to ascend above the manual adjustments, measurement problems and to tame the quick voltage and current transients.

This thesis presents the state of the design methods in power electronics, focusing on the transistor modeling and packaging design and identifying the crucial points for further development.

The thesis presents an approach developed to interface accurate circuit simulators with modern programming languages. The developed interface integrates solver adaptation methods to ensure computational convergence and reliable simulation, and is then used to tackle automated gate impedance design and current sharing optimization tasks.

The thesis expands further, integrating the layout design and tackling the two most computationally heavy parts - layout parasitics extraction and semiconductor device modeling. The process surrogating approach utilizing deep neural networks is presented, drastically decreasing the computational cost of parasitics equivalent circuit extraction. As for the semiconductor device modeling, a new approximate modeling approach is described to improve convergence and decrease the computational cost.