Supervisor:
Stig Munk-Nielsen

Co-Supervisor:
Hongbo Zhao

Assessment Committee:
Sanjay Chaudhary (Chair)
Dr. Krishna Vasudevan, IIT Madras
Dr. Arnold Knott, DTU

Moderator:
Michael Møller Bech

Abstract:

Silicon carbide (SiC) MOSFETs operating at medium voltages offer the efficiency, power density, and switching performance required for next‑generation renewable‑energy converters. However, their high voltage levels and rapid switching transitions introduce stringent requirements on gate‑driver insulation, parasitic minimization, and stability to ensure reliable operation.

This thesis addresses four key challenges in MV SiC‑MOSFET gate driving—robust high‑voltage insulation, low common‑mode capacitance, stable auxiliary‑power regulation, and mitigation of gate‑loop parasitics—through a combined digital‑and‑experimental approach. A novel core‑series‑coupling planar transformer provides 11.5 kV partial‑discharge inception voltage with only 0.42 pF coupling capacitance, while an open‑loop regulator maintains stable output voltage across varying loads. Experimental double‑pulse tests in a 10 kV/30 A half‑bridge module demonstrate switching speeds up to 133.9 V/ns. A small‑signal half‑bridge model incorporating parasitic capacitances identifies four oscillation loops—capacitive coupling, DC‑bus inductance, gate, and grounding—and guides practical mitigation strategies. Finally, for paralleling MV SiC‑MOSFETs, a single‑driver architecture with discrete Miller‑clamp circuits is shown to suppress crosstalk while ensuring clear switching transient.

By combining modeling with hardware validation, this work delivers design guidelines that accelerate reliable integration of MV SiC‑MOSFETs into power‑conversion systems with minimal physical prototyping.